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DIGITAL EXCESS LOOP DELAY COMPENSATION TECHNIQUE WITH EMBEDDED TRUNCATOR FOR CONTINUOUS-TIME DELTA–SIGMA MODULATORS

Abstract

Introduction: In communication systems, rapidly increasing demands on system bandwidth lead to design challenges for the analogue front end. High-speed high-performance analogue-to-digital converters thus became necessary. The continuous-time delta–sigma (ΔΣ) modulator (CT-DSM) is a good candidate due to its mid-to-high resolution, high speed and its intrinsic anti-aliasing filter. Recent work has raised the sampling rate to the gigahertz range in CT-DSMs [1], using advanced processes. When a high sampling rate is used, the excess loop delay (ELD) caused by the regeneration time of the internal quantiser and of the control circuit in the internal feedback path including dynamic element matching (DEM), impairs the modulator’s stability. Hence, ELD compensation has become essential in high-speed CT-DSM design [2]. To avoid the design difficulty in the analogue domain, several authors implemented ELD compensation in the digital domain [1–3]. As shown in Fig. 1a, the ELD compensation path can be realised entirely in the digital domain [3]. The structure described in [2] requires more comparators and DAC levels; the compensation can also be realised by shifting the reference levels of the internal quantiser as shown in Fig. 1b

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PBM_UuI50

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