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A MULTIPLEXER-BASED DIGITAL PASSIVE LINEAR COUNTER (PLINCO)

Abstract

A ones adder is an important circuit block that is required in many varying applications. This work proposes a design that largely relies on passive transmission-gate multiplexers. Many variations are suggested that can inherently generate a thermometer coded output or one-hot encoded output. The proposed structure has area and power that increases with order n2 for a n number of inputs. A folding technique is then suggested that reduces the area/power to order n log(n). The folded PLINCO also has a cell-based structure that aids in layout and makes it possible to be added to a digital standard cell library.

Material Code

PBM_jDRtV

Reference

[1] F. Kaess et al., "New Encoding Scheme For High-Speed Flash ADC's," Circuits and Systems, IEEE International Symposium on, pp. 5-8, June 1997 [2] R. J. Van de Plassche, Integrated analog-to-digital and digital-to-analog converters, Kluwer Academics Publishers, ch. 3, 1994. [3] E. Säll, M. Vesterbacka, and K. O. Andersson, "A Study of Digital Decoders in Flash Analogto-Digital Converters," Circuits and Systems, IEEE International Symposium on, pp. 129-132, May 2004. [4] G. Moore, "Cramming More Components onto Integrated Circuits," Electronics, vol. 38, no. 8, 1965, pp. 114-117. [5] B. Spencer, L. Wilson, and R. Doering, "The Semiconductor Technology Roadmap," Future Fab Int'l, vol. 18, Jan. 12, 2005. [6] T.-C. Chen, "Overcoming Research Challenges for CMOS Scaling: Industry Directions," Solid-State and Integrated Circuit Tech., Inter. Conf. on, pp. 4-7, October 2006. [7] C. Donovan and M. P. Flynn, "A `digital' 6-bit ADC in 0.25 μm CMOS," Solid-State Circuits, IEEE J. of, vol. 37, no. 3, pp. 432-437, Mar. 2002. [8] D. C. Daly and A. P. Chandrakasan, "A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy," Solid-State Circuits Conf., IEEE Inter., pp. 554-555, 635, February 2008.

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